A fuse is a device that is initially in a conductive state and becomes non-conductive when blown. In contrast, an antifuse is non-conductive in the native unprogrammed state and becomes conductive when programmed, hence the name antifuse. Antifuse used in integrated circuits is commonly constructed with a thin dielectric layer sandwiched between two conductors. To program an antifuse, a high voltage is applied between the two conductors. This leads to a physical and permanent breakdown of the thin dielectric layer and the formation of a current conduction path between the two conductors. Antifuse can thus be used as a memory element. Programmed state of an antifuse represents data “1” and unprogrammed state “0” or vice versa. Once programmed, antifuse memory cannot revert to unprogrammed state, i.e., it is a one-time programmable (OTP) memory. Antifuse retains conductive or non-conductive state even after the power is turned off, rendering the data non-volatile. As such, antifuse memory is a non-volatile OTP memory.
Use of antifuse OTP memory includes storing program codes, security codes and trimming data of analog circuits in various integrated circuits. Its application includes consumer, industrial, automotive electronics, and internet-of-things (IoT). For these applications, an antifuse OTP memory capable of high-speed and reliable operation with high-density and low-power consumption is desired.
Antifuse OTP memory is one of the several semiconductor OTP memory types available today, namely, electrical fuse, mask read-only memory (ROM), floating gate memory and antifuse memory. Due to its small bit cell size, good reliability, user programmability and easy integration and scaling with the complementary metal-oxide-semiconductor (CMOS) process, popularity of antifuse memory as an OTP memory embedded in integrated circuit chips is increasing. The mainstream antifuse OTP memory manufactured today uses metal-oxide-semiconductor (MOS) capacitor as the antifuse element. In the conventional one-transistor one-capacitor (1T1C) antifuse memory cell, MOS capacitor is connected to an access device, typically a metal-oxide-semiconductor field-effect-transistor (MOSFET) to form an antifuse memory bit cell. This is schematically illustrated in FIG. 1A, a prior art. In FIG. 1A, PL is the program line where a high voltage is applied during programming, WL is the word line and BL is the bit line of the memory cell. FIG. 1B illustrates an exemplary cross-sectional view of 1T1C cell from a standard CMOS process. Starting material in FIG. 1B is the P-type silicon substrate 100. Source/drain 102, gate dielectric 104 and gate polysilicon 106 form the access transistor. MOS capacitor shown inside a circle in FIG. 1A and FIG. 1B comprises gate polysilicon 106, gate dielectric 104 and the channel region, which is the silicon substrate 100. MOS capacitor is connected to the access transistor by the MOSFET drain diffusion 102 on one end, and open-circuited at the other end with the gate polysilicon terminated on shallow trench isolation (STI).
In a standard CMOS process, source/drain and gate of a MOSFET are of the same conductivity type and the MOSFET channel region, i.e., silicon under the gate polysilicon is of the opposite conductivity type. This is seen in FIG. 1B, a cross-section view of the conventional 1T1C cell, wherein the source/drain 102 and gate 106 of the access transistor are N-type and the channel region 100 is P-type. Likewise, MOS capacitor shown in FIG. 2A, reproduced from FIG. 1B, has the gate 206 and the source/drain 202 doped in N-type and the channel region 200 under the gate polysilicon 206 doped in P-type. FIG. 2A highlights the current conduction path 205 formed at the ruptured spot in the gate dielectric 204 is not ohmic but takes the form of a PN junction diode because of the opposite conductivity types of the gate polysilicon 206 and capacitor channel 200.
Referring again to FIG. 2A, it should be pointed out the diode created at the connection 205 in a standard CMOS process is a polysilicon-to-silicon diode. Because of the low mobility of electrons and holes in polysilicon and the high interface trap density at the polysilicon grain boundaries, the electrical characteristics of polysilicon-to-silicon diode may be substantially worse than those of a PN junction diode formed in the single-crystal silicon substrate. FIG. 2B shows DC equivalent circuit of a PN junction diode wherein Rf 210 is the diode resistance in the forward mode, Rr 212 is the diode resistance in the reverse mode and the diode symbol 214 represents an ideal diode for which Rf is zero and Rr is infinity. Diodes formed in the single-crystal silicon substrate are, though not ideal, high quality diodes with low Rf values as low as a few ohms and very high Rr values well above 1×1012 ohms. By contrast, Rf of a polysilicon-to-silicon diode may be much higher and Rr may be much lower as much as by several orders of magnitude. Furthermore, uniformity of polysilicon-to-silicon diodes may be poor, causing a large variation of Rf and Rr among diodes. FIG. 3 schematically illustrates the current-vs.-voltage characteristics of polysilicon-to-silicon diodes and diodes formed in the silicon substrate. Forward currents of polysilicon-to-silicon diodes 304 are lower and more scattered than those of diodes formed in the silicon substrate 302. For example, the forward currents of the polysilicon-to-silicon diodes may range from 10 micro ampere (uA) to 500 uA at a forward bias voltage of 1 volt (V) when the forward current of the diodes formed in the silicon substrate is 1 milli ampere (mA). Reverse leakage currents of polysilicon-to-silicon diodes 308 are higher and more scattered than those of diodes formed in the silicon substrate 306. For example, reverse leakage currents of the polysilicon-to-silicon diodes may range from 10 pico ampere (pA) to 1 nano ampere (nA) at a forward bias voltage of 1.8V when the reverse leakage current of the diodes formed in the silicon substrate is 10 femto ampere (fA). It is to be mentioned since reverse leakage currents 306 and 308 are much smaller than the forward currents 302 and 304, different scales are used in FIG. 3 for the positive Y axis and for the negative Y axis in order to show and compare the forward and reverse currents of these diodes in a single plot. The shortcomings of polysilicon-to-silicon diodes shown in FIG. 3 are an inherent limitation to building a high-performance high-density antifuse OTP memory array.
An antifuse OTP memory array featuring a small bit cell has been disclosed in a prior art found in U.S. Pat. No. 8,330,189. The OTP memory therein uses polysilicon-to-silicon diode as the bit-cell access device and has a cross-point array architecture. The buried bit-line cell structure employed therein enables a small bit cell size and cross-point array architecture. However, it causes a high and varying bit-cell series resistance among bit cells connected to the same metal bit line. In addition, use of polysilicon-to-silicon diode as the access device makes it more challenging to bring cell-to-cell variation under control. The problem of a high and varying series resistance stemming from the buried bit-line cell of U.S. Pat. No. 8,330,189 is solved in U.S. Pat. No. 9,406,397 wherein each bit cell is directly connected to the metal bit line. However, use of polysilicon-to-silicon diode as access device and cell-to-cell variation associated with it may limit its merit. To build a high-performance and high-density antifuse OTP memory array, it is crucial to have a tight control of electrical characteristics among cells. The objective of the present invention is to eliminate the shortcomings inherent in the prior arts, specifically a large cell-to-cell variation of the electrical characteristics, and thereby realize a high-performance and high-density antifuse OTP memory.